Lead Digital Verification Engineer

Cadence

Edinburgh, Scotland, United Kingdom
System verilog and assertions
Metric driven verification (mdv)
Constrained-random verification techniques
The Cadence Silicon Systems Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets

Job Summary

  • The Cadence Silicon Systems Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets.
  • As a member of the Central Engineering Team within SSG, you will be responsible for defining and supporting the adoption of cutting-edge verification tools and methodologies with a focus on AI and Machine Learning.
  • Competitive salary, 25 days holiday per year, Private Medical and Dental plans, Income Protection and Life Insurance, Group Personal Pension Plan, Cycle to work scheme and gym subsidy, 5 days paid time to volunteer, Employee Stock Purchase Plan.

Matching Summary

The Cadence Silicon Systems Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets.

Skills & Requirements

Must-have

  • System Verilog and assertions
  • Metric Driven Verification (MDV)
  • constrained-random verification techniques
  • UVM verification environments
  • generative AI tools

Nice-to-have

  • AI agent development
  • Methodology development
  • change management experience
  • Functional Safety Verification
  • Low Power Verification

Key Requirements

  • 4+ years experience in microelectronics/EDA
  • Degree in Electrical/Electronic Engineering, Microelectronics, or related
  • Excellent spoken and written English

Work Rights

Not specified

Tailored Resume

Cover Letter