Senior Static Timing Analysis (sta) Developer

Altera Corporation

San Jose, California, United States
Base: $178.9k - $259.0k usd; bonus/equity: incenti...
10+ years eda software development experience
Deep understanding of sta algorithms and data structures
Strong c/c++ development skills for large-scale codebases
This role involves architecting next-generation timing analysis engines capable of handling massive SoC designs with over 100 million gates

Job Summary

  • This role involves architecting next-generation timing analysis engines capable of handling massive SoC designs with over 100 million gates.
  • The successful candidate will optimize PPA-critical components and implement advanced data structures to ensure best-in-class accuracy and runtime performance.
  • Employees will have the opportunity to shape industry-leading STA technology used in advanced semiconductor design within a collaborative technical environment.

Matching Summary

This role involves architecting next-generation timing analysis engines capable of handling massive SoC designs with over 100 million gates.

Salary

Base: $178.9K - $259.0K USD; Bonus/Equity: Incentive opportunities available based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • 10+ years EDA software development experience
  • Deep understanding of STA algorithms and data structures
  • Strong C/C++ development skills for large-scale codebases
  • Experience with multi-threading and memory optimization
  • Ability to debug complex timing and infrastructure issues

Nice-to-have

  • Commercial STA tool development experience
  • Familiarity with ASIC/FPGA design flows
  • Background supporting customer tape-outs
  • Knowledge of disk-caching strategies
  • Experience with distributed computing techniques

Key Requirements

  • 10+ years of experience in EDA software development
  • Eligibility for required U.S. export authorizations

Work Rights

Must be eligible for required U.S. export authorizations

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