Senior/ DFT Engineer (ASIC Design)

ETHOS SEARCH ASSOCIATES PTE. LTD.

Singapore
Dft implementation on hard-ips
Scan compression and atpg tools
Verilog logic design and synthesis
The role involves developing and implementing complex DFT schemes on hard-IPs in FPGAs alongside the design team

Job Summary

  • The role involves developing and implementing complex DFT schemes on hard-IPs in FPGAs alongside the design team.
  • Candidates will be responsible for debugging scan and MBIST pattern issues to root cause problems during post-silicon validation.
  • The position requires proficiency with industry-standard DFT tools including ATPG for stuck-at, at-speed, and path-delay fault models.

Matching Summary

Match Score: 85

The role involves developing and implementing complex DFT schemes on hard-IPs in FPGAs alongside the design team.

Skills & Requirements

Must-have

  • DFT implementation on hard-IPs
  • Scan compression and ATPG tools
  • Verilog logic design and synthesis
  • Post-silicon debug and ATE bench setup
  • Linux environment scripting

Nice-to-have

  • MBIST knowledge
  • FPGA synthesis experience
  • Yield enhancement skills
  • Cross-continent collaboration
  • Self-motivated team player

Key Requirements

  • BS or MS in Electrical/Electronic/Computer Engineering
  • 1+ years of experience as a DFT engineer
  • Experience with Scan and Scan Compression at IP and SoC level

Work Rights

Not specified

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