Asic Engineering Technical Leader - Dft

Cisco UK

San Jose, California, United States
Base: $183,800.00 to $263,600.00; bonus/equity: el...
7+ years asic dft experience
Jtag protocols and scan architecture
Memory bist and boundary scan
This role involves leading the implementation of Hardware Design-for-Test features for Cisco's Silicon One architecture across complex networking chips

Job Summary

  • This role involves leading the implementation of Hardware Design-for-Test features for Cisco's Silicon One architecture across complex networking chips.
  • The successful candidate will drive DFT requirements early in the design cycle and collaborate with front-end RTL and backend physical design teams.
  • Employees are eligible for competitive compensation including base salary, potential equity grants, and comprehensive benefits like medical insurance and paid time off.

Matching Summary

This role involves leading the implementation of Hardware Design-for-Test features for Cisco's Silicon One architecture across complex networking chips.

Salary

Base: $183,800.00 to $263,600.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), and paid leave included

Skills & Requirements

Must-have

  • 7+ years ASIC DFT experience
  • Jtag protocols and Scan architecture
  • Memory BIST and boundary scan
  • ATPG and EDA tools expertise
  • Gate level simulation debugging
  • Post-silicon validation experience

Nice-to-have

  • Verilog design for custom DFT logic
  • System Verilog Logic Equivalency checking
  • Test Static Timing Analysis skills
  • P1687 standard familiarity
  • Collaboration with multi-functional teams

Key Requirements

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • Minimum 7 years of relevant industry experience
  • Experience with TestMax, Tetramax, Tessent, and PrimeTime tools

Work Rights

Not specified

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