Senior Static Timing Analysis (sta) Developer

Altera Digital Health

San Jose, California, United States
Base: $178.9k - $259.0k usd; bonus/equity: incenti...
Sta algorithms and data structures
Large-scale eda software development
Performance-driven optimization
Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms

Job Summary

  • Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.
  • Identify and eliminate runtime bottlenecks, optimize PPA-critical components, and implement advanced data structures for extremely large IC designs.
  • Support customer tape-outs by ensuring STA robustness, accuracy, and runtime efficiency, and contribute to product roadmap discussions.

Matching Summary

Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.

Salary

Base: $178.9K - $259.0K USD; Bonus/Equity: Incentive opportunities; Benefits: Not specified

Skills & Requirements

Must-have

  • STA algorithms and data structures
  • large-scale EDA software development
  • performance-driven optimization
  • C/C++ development skills
  • multi-threading and memory optimization

Nice-to-have

  • customer tape-out support
  • disk-caching strategies
  • distributed computing techniques

Key Requirements

  • 10+ years of experience in EDA software development
  • Experience with multi-threading, memory optimization
  • Proven ability to debug complex issues

Work Rights

Eligible for U.S. export authorizations

Tailored Resume

Cover Letter