Physical Design Engineer

Cisco UK

Rtl to gdsii implementation experience
Gate-level netlist synthesis and pnr
Static timing analysis (sta) expertise
The team is redefining silicon technology by managing full chip physical implementation from RTL to GDSII

Job Summary

  • The team is redefining silicon technology by managing full chip physical implementation from RTL to GDSII.
  • Engineers will optimize designs to achieve industry-leading power, performance, and area metrics while ensuring design integrity.
  • Candidates will work hand-in-hand with Front-End teams to transform cutting-edge designs into industry-leading silicon solutions.

Matching Summary

The team is redefining silicon technology by managing full chip physical implementation from RTL to GDSII.

Skills & Requirements

Must-have

  • RTL to GDSII implementation experience
  • Gate-level netlist synthesis and PnR
  • Static Timing Analysis (STA) expertise
  • Physical verification and signoff closure
  • Electromigration and IR-drop analysis

Nice-to-have

  • Mentorship and collaborative culture
  • Scripting proficiency in Tcl or Python
  • Block-level synthesis knowledge
  • LVS and DRC verification techniques
  • Automation and efficiency improvements

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Minimum of 3 years of experience in ASIC design
  • First-hand experience with Synopsys and Cadence tools

Work Rights

Not specified

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