Asic Engineer | Physical Design | 4+ Years |

Cisco UK

Bangalore, India
Physical design
Rtl to gds flow
Timing closure
Join the Cisco SiliconOne team to craft groundbreaking Enterprise and Service Provider solutions by developing complex chips

Job Summary

  • Join the Cisco SiliconOne team to craft groundbreaking Enterprise and Service Provider solutions by developing complex chips.
  • Drive the backend process through the entire RTL 2 GDS Implementation flow with a focus on performance and die size optimization.
  • Work closely with various teams to improve physical design methodologies and streamline physical design work.

Matching Summary

Join the Cisco SiliconOne team to craft groundbreaking Enterprise and Service Provider solutions by developing complex chips.

Skills & Requirements

Must-have

  • Physical Design
  • RTL to GDS flow
  • Timing closure
  • Power Integrity Analysis
  • Physical Verification
  • Advanced process nodes

Nice-to-have

  • Automation scripts within STA tools
  • Creative solutions for implementation issues
  • Methodology development
  • Startup culture with top-tier benefits

Key Requirements

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 5+ years of experience
  • Experience with large designs (>100M gates)
  • Experience with sub 16/14/7/5/3nm technologies

Work Rights

Not specified

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