R&d Engineer Ic Design 4

Broadcom

Austin, TX, United States
Base: $51.92 - 83.07 ph; bonus/equity: discretiona...
Asic design and implementation flow
Verilog simulation and debugging
Synopsys design compiler or cadence rtl compiler
You will be responsible for the front end design and verification of design blocks for ASIC cores including architecture definition and logic design

Job Summary

  • You will be responsible for the front end design and verification of design blocks for ASIC cores including architecture definition and logic design.
  • Broadcom offers a competitive and comprehensive benefits package including medical, dental, vision plans, 401(K) with company matching, and an Employee Stock Purchase Program.
  • Broadcom is an equal opportunity employer and considers qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, or other protected characteristics.

Matching Summary

You will be responsible for the front end design and verification of design blocks for ASIC cores including architecture definition and logic design.

Salary

Base: $51.92 - 83.07 per hour; Bonus/Equity: Discretionary annual bonus; Benefits: Medical, dental, vision, 401(K), ESPP, paid leave

Skills & Requirements

Must-have

  • ASIC design and implementation flow
  • Verilog simulation and debugging
  • Synopsys Design Compiler or Cadence RTL compiler
  • Timing analysis with Primetime
  • Formal verification tools
  • TCL/Perl scripting
  • Version control systems

Nice-to-have

  • Ability to work independently and in large teams
  • Familiarity with DFT and scan methodology
  • Experience with power analysis of RTL and gate level netlists

Key Requirements

  • 6+ years experience with MS or 8+ years with BS in ASIC design
  • BS/MS in Electrical or Computer Engineering or equivalent
  • Experience with RTL synthesis and timing closure

Work Rights

Not specified

Tailored Resume

Cover Letter