Base: $141,900.00-$189,200.00; bonus/equity: not s...
Onsite
7+ years digital logic design experience
Verilog/systemverilog rtl proficiency
Pcie gen4/gen5/gen6 protocol expertise
Teledyne LeCroy is seeking a Staff Logic Design Engineer to join their high-speed Protocol Team in Milpitas, CA. The ideal candidate should have extensive experience in digital logic design, particularly with FPGA or ASIC development, and familiarity with high-speed protocols such as PCIe and USB
Job Summary
This role involves architecting and implementing high-performance digital logic for real-time decoding of high-speed protocols like PCIe and USB.
Candidates will work on cutting-edge FPGA-based systems to validate technologies used in data centers, AI/ML, and networking sectors.
The position offers a collaborative, fast-paced environment within a global leader in protocol analysis and test solutions.
Matching Summary
Match Score: 85
Teledyne LeCroy is seeking a Staff Logic Design Engineer to join their high-speed Protocol Team in Milpitas, CA. The ideal candidate should have extensive experience in digital logic design, particularly with FPGA or ASIC development, and familiarity with high-speed protocols such as PCIe and USB.
Salary
Base: $141,900.00-$189,200.00; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
7+ years digital logic design experience
Verilog/SystemVerilog RTL proficiency
PCIe Gen4/Gen5/Gen6 protocol expertise
Xilinx Versal or Intel Agilex FPGA development
SystemVerilog/UVM verification methodology
High-speed serial protocol debugging skills
Nice-to-have
Python or Tcl scripting for automation
Experience with AXI interconnects
Hardware/software co-design background
Prior work in test and measurement environments
Familiarity with SERDES link training
Strong team collaboration spirit
Key Requirements
BS in EE, CS, or Computer Engineering required
MS in EE is preferred
Hands-on experience with Vivado or Quartus toolchains