Principal Fpga / Rtl Design Engineer - Signal Processing
Silvus Technologies
Irvine, CA, United States
$165,000—$250,000 usd py
On-site
Rtl coding, simulation, and test bench development
Fpga synthesis and timing closure
Hardware verification and troubleshooting
Silvus Technologies is seeking a Principal FPGA/RTL Design Engineer specialized in signal processing to join their Irvine, CA team. The ideal candidate will possess extensive experience in RTL design and FPGA implementation, particularly in the context of wireless communication systems
Job Summary
The company is a leading provider of advanced MANET and MIMO communications systems, reshaping mesh network technology for mission-critical applications.
The role involves participating in all aspects of the research and development process from concept to field deployment, implementing novel signal processing algorithms for MIMO wireless networking products.
This is a 100% onsite position in Irvine, CA, requiring a U.S. Citizen due to government contracts.
Matching Summary
Match Score: 85
Silvus Technologies is seeking a Principal FPGA/RTL Design Engineer specialized in signal processing to join their Irvine, CA team. The ideal candidate will possess extensive experience in RTL design and FPGA implementation, particularly in the context of wireless communication systems.
Salary
$165,000—$250,000 USD
Skills & Requirements
Must-have
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
Fixed point binary arithmetic and DSP designs
Verilog and System-Verilog
Xilinx FPGAs, SoCs, and Vivado IDE
Nice-to-have
MATLAB skills
Scripting languages like Perl and Python
Wireless communication systems experience
Key Requirements
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of RTL design and FPGA implementation experience