Principal Design Engineer

Cadence

Finfet technology layouts
3nm/5nm/7nm technology nodes
6+ years custom layout experience
The candidate will own and lead major blocks of Memory PHY Layout design while performing hands-on design of critical analog and high-speed layout blocks

Job Summary

  • The candidate will own and lead major blocks of Memory PHY Layout design while performing hands-on design of critical analog and high-speed layout blocks.
  • Candidates must have specific exposure to advanced technology nodes including 3nm, 5nm, and 7nm FinFet technologies.
  • The role involves coordinating design work with circuit leads, layout contractors, and team members while participating in layout reviews.

Matching Summary

The candidate will own and lead major blocks of Memory PHY Layout design while performing hands-on design of critical analog and high-speed layout blocks.

Skills & Requirements

Must-have

  • FinFet technology layouts
  • 3nm/5nm/7nm technology nodes
  • 6+ years custom layout experience
  • Memory PHY Layout design ownership

Nice-to-have

  • High-speed analog mixed-signal layout
  • Leadership of major design blocks
  • Experience coordinating with contractors

Key Requirements

  • 6+ years of experience in custom layout
  • Expertise in FinFet technology layouts
  • Knowledge of 3nm/5nm/7nm nodes

Work Rights

Not specified

Tailored Resume

Cover Letter