Full Chip Timing Modeling And Integration Engineer
Altera
Penang, Malaysia
Static timing analysis (sta)
Liberty verilog design constraints sdc
Soc development experience
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies
Job Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Candidates will collaborate with cross-functional teams to define timing modeling strategies, generate high-level models, and validate them against design requirements.
This position requires strong interpersonal skills to negotiate technical trade-offs and solve critical design issues within aggressive schedules.
Matching Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Skills & Requirements
Must-have
Static Timing Analysis (STA)
Liberty Verilog Design Constraints SDC
SoC development experience
Python and Tcl script writing
AOCV POCV silicon modeling concepts
Nice-to-have
Multi voltage domain experience
FPGA DDR PCIe Ethernet HBM architecture
DFT functional constraint management
Complex multi-site team collaboration
Key Requirements
BS/MS Degree in Electrical Engineering or related field