Staff Engineer, Design Verification

Analog Devices

Milan, Italy
System verilog and uvm
Constrained random functional verification
Functional coverage and assertions
The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center

Job Summary

  • The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center.
  • Candidate will work with the latest verification methodologies on designs ranging from individual blocks to sub-system level verification.
  • Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Matching Summary

The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center.

Skills & Requirements

Must-have

  • System Verilog and UVM
  • constrained random functional verification
  • functional coverage and assertions
  • gate-level simulations and debugging
  • development of verification plans
  • verification environments from scratch

Nice-to-have

  • technically mentoring and coaching junior engineers
  • highly independent, proactive, and result-oriented
  • strong interpersonal, teamwork, and communication skills

Key Requirements

  • 8+ years of experience in digital design
  • 3 years in digital verification
  • Bachelor's or Master’s degree in Electronics Engineering
  • Expertise in Verilog, System Verilog, UVM
  • object-oriented programming, scripting, and automation
  • Experience with PMBus, SPI, OTP/MTP, and I2C protocols

Work Rights

Not specified

Tailored Resume

Cover Letter