Principal Electrical Engineer: Fpga

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FT WAYNE, Indiana, United States of America
Base: 107,500 usd - 204,500 usd; bonus/equity: not...
Hybrid
Fpga/asic design vhdl/verilog
Fpga/asic verification systemverilog
Amd xilinx altera microchip devices
The job posting is for a Principal Electrical Engineer specializing in FPGA design at Raytheon in Fort Wayne, Indiana. The role requires a strong background in FPGA/ASIC design and verification, with responsibilities spanning the entire product lifecycle, and includes a focus on leadership and collaboration within a multidisciplinary team

Job Summary

  • The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems.
  • In this role, you will leverage advanced technologies to create cutting-edge solutions for sensor and effector products.
  • This position offers relocation based on candidate eligibility and requires a Secret DoD security clearance.

Matching Summary

Match Score: 85

The job posting is for a Principal Electrical Engineer specializing in FPGA design at Raytheon in Fort Wayne, Indiana. The role requires a strong background in FPGA/ASIC design and verification, with responsibilities spanning the entire product lifecycle, and includes a focus on leadership and collaboration within a multidisciplinary team.

Salary

Base: 107,500 USD - 204,500 USD; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) match, PTO

Skills & Requirements

Must-have

  • FPGA/ASIC design VHDL/Verilog
  • FPGA/ASIC verification SystemVerilog
  • AMD Xilinx Altera Microchip devices
  • AMD Vivado Altera Quartus Libero tools
  • Integration and debug in lab environment
  • Timing closure and constraint development

Nice-to-have

  • AI/ML inference on FPGA
  • UVM constrained random verification
  • High Level Synthesis HLS experience
  • Embedded systems using ARM Microblaze
  • Vector processors and/or GPUs
  • Mentorship of junior engineers

Key Requirements

  • Minimum 8 years relevant experience
  • FPGA/ASIC design or verification experience
  • Experience with specific FPGA vendors and tools
  • Hands-on integration and debug experience
  • Experience with timing closure and constraints
  • Experience with source code management and reviews
  • Ability to obtain and maintain U.S. government security clearance

Work Rights

U.S. citizenship required for security clearance

Tailored Resume

Cover Letter