Senior Design Verification Engineer

Altera Corporation

San Jose, California, United States
Base: $142.6k - $206.5k usd; bonus/equity: incenti...
9+ years verification collateral experience
7+ years ethernet pcie cxl protocol verification
Uvm fluency and complex coverage driven environments
The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios

Job Summary

  • The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios.
  • Candidates must possess deep expertise in high-speed protocols such as Ethernet, PCIe, and CXL to ensure robust functionality.
  • The position requires developing comprehensive test plans, creating directed and random test cases, and achieving strict coverage metrics.

Matching Summary

The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios.

Salary

Base: $142.6k - $206.5k USD; Bonus/Equity: Incentive opportunities available based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • 9+ years verification collateral experience
  • 7+ years Ethernet PCIe CXL protocol verification
  • UVM Fluency and complex coverage driven environments
  • High-speed transceiver protocol validation
  • RTL design debugging and testbench development

Nice-to-have

  • Cross-functional team collaboration skills
  • Advanced verification tool development
  • IP bring-up on FPGA development kits

Key Requirements

  • BS/MS in Electrical or Computer Engineering
  • 9+ years industry experience in verification
  • 7+ years with UVM and constraint-based testing
  • Eligibility for US export authorizations

Work Rights

Must be eligible for required US export authorizations

Tailored Resume

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