Emulation Design Engineer

Cadence

Systemverilog for synthesizable rtl design
Palladium and protium emulation platforms
Pcie ucie ethernet ddr usb protocol experience
This role focuses on developing and integrating high-speed interface subsystems in Emulation Platforms

Job Summary

  • This role focuses on developing and integrating high-speed interface subsystems in Emulation Platforms.
  • The engineer will lead the design and deployment of Emulation PHY logic for platforms including Palladium and Protium.
  • Candidates must have strong experience with system-level design and communication standards such as PCIe, UCIe, and Ethernet.

Matching Summary

This role focuses on developing and integrating high-speed interface subsystems in Emulation Platforms.

Skills & Requirements

Must-have

  • SystemVerilog for synthesizable RTL design
  • Palladium and Protium emulation platforms
  • PCIe UCIe Ethernet DDR USB protocol experience
  • C and Python scripting for automation
  • Analog Mixed Signal to emulation model conversion

Nice-to-have

  • Experience building emulatable AVIP solutions
  • Strong analytical and problem-solving skills
  • Excellent communication and leadership abilities
  • Familiarity with end-to-end verification flows
  • Experience in system prototyping and bring-up

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 5-16 years of relevant experience
  • Hands-on experience with emulation platforms like Zebu or HAPS

Work Rights

Not specified

Tailored Resume

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