The role requires a candidate with strong SystemVerilog and UVM expertise to build scalable test benches for AXI and NOC/Crossbar architectures
Job Summary
The role requires a candidate with strong SystemVerilog and UVM expertise to build scalable test benches for AXI and NOC/Crossbar architectures.
Candidates must be able to work in a fast-paced startup environment with minimal documentation while ensuring coverage closure and performance regression.
The position is fully onsite in San Jose, California, requiring daily or weekly progress reporting directly to the client.
Matching Summary
The role requires a candidate with strong SystemVerilog and UVM expertise to build scalable test benches for AXI and NOC/Crossbar architectures.
Skills & Requirements
Must-have
Strong SV/UVM scale test bench expertise
AXI and NOC/Crossbar protocol knowledge
Performance regression and triage experience
Coverage closure skills
Amazon tools and flows proficiency
Nice-to-have
Make/Perl/Python scripting abilities
Experience in startup mode environments
Effective customer reporting capabilities
Key Requirements
Bachelor's degree in Electrical or Computer Engineering
Master's degree in Electrical or Computer Engineering
Minimum 8 years of ASIC verification experience
Must be available for Day-1 Onsite work in San Jose CA