Senior Principal Design Engineer

Cadence

10-15 years post silicon validation experience
High speed serdes protocol expertise
Oscilloscopes network analyzer bert usage
The role involves leading the development of validation infrastructure for Cadence's High Speed SERDES Test chips

Job Summary

  • The role involves leading the development of validation infrastructure for Cadence's High Speed SERDES Test chips.
  • Candidates must possess deep experience in physical layer electrical validation on protocols like PCIe, USB, or Ethernet.
  • Cadence offers a collaborative culture with multiple avenues for learning and development to support employee well-being.

Matching Summary

The role involves leading the development of validation infrastructure for Cadence's High Speed SERDES Test chips.

Skills & Requirements

Must-have

  • 10-15 years post silicon validation experience
  • High speed SERDES protocol expertise
  • Oscilloscopes Network Analyzer BERT usage

Nice-to-have

  • Experience managing small teams of 2+
  • Analog PLL FPGA PCB design skills
  • Verilog RTL coding proficiency

Key Requirements

  • B.Tech degree with 10-15 years experience
  • M.Tech degree with 8-13 years experience
  • Hands-on lab equipment operation skills

Work Rights

Not specified

Tailored Resume

Cover Letter