As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment
Job Summary
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Develop and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Matching Summary
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Skills & Requirements
Must-have
Hierarchical DFT architecture
Scan compression
Boundary Scan
MBIST
In-System Test (IST)
Power-on self-test (POST)
ATPG (Stuck-at, Transition, Path Delay)
Memory & Logic BIST
FinFET nodes (7nm, 5nm, or below)
DFT in multi-voltage/power-gated designs
Nice-to-have
Seamless software integration
High-performance architecture
Minimize area overhead and power impact
Root-cause silicon failures
Optimize test time
Key Requirements
12+ years in DFT
2+ years in a leadership or principal role
Mastery of industry-standard tools (Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus)
Deep expertise in MBIST, SCAN, IJTAG, and boundary scan