This 6-month contract role offers hands-on experience working on industry-leading programmable logic devices and SoC platforms
Job Summary
This 6-month contract role offers hands-on experience working on industry-leading programmable logic devices and SoC platforms.
The engineer will develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems while writing self-checking testbenches.
Candidates must be eligible for any required U.S. export authorizations to work on next-generation FPGA products.
Matching Summary
This 6-month contract role offers hands-on experience working on industry-leading programmable logic devices and SoC platforms.
Salary
Base: $100-105K USD; Bonus/Equity: Incentive opportunities available; Benefits: Not specified
Skills & Requirements
Must-have
RISC-V design experience
SystemVerilog and Verilog proficiency
UVM-based verification environments
Constrained random verification skills
Simulation tools like VCS or QuestaSim
Nice-to-have
Experience with AXI protocol verification
Familiarity with Intel Quartus Prime or Vivado
Python, Perl, Tcl, or C scripting skills
Knowledge of HLS and AI/ML accelerators
Formal verification concepts exposure
Key Requirements
Bachelor's Degree in Computer or Electrical Engineering