Senior/ Staff Chip Top Physical Design Engineer

Astera Labs

Israel
On-site
Soc top-level physical design
Floor-planning, place & route, cts
Power integrity and timing/physical signoff
Astera Labs is looking for a Senior/Staff Chip Top Physical Design Engineer to join its new R&D center in Israel. The role requires extensive experience in semiconductor chip design, particularly in deep-submicron processes, and emphasizes collaboration across various engineering teams to optimize performance and power efficiency

Job Summary

  • Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale.
  • You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters.
  • You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria.

Matching Summary

Match Score: 85

Astera Labs is looking for a Senior/Staff Chip Top Physical Design Engineer to join its new R&D center in Israel. The role requires extensive experience in semiconductor chip design, particularly in deep-submicron processes, and emphasizes collaboration across various engineering teams to optimize performance and power efficiency.

Skills & Requirements

Must-have

  • SoC Top-level physical design
  • Floor-planning, Place & Route, CTS
  • Power Integrity and Timing/Physical signoff
  • RTL2GDS flows
  • Synopsys Fusion Compiler/ICC2 or Cadence Innovus

Nice-to-have

  • High-speed interfaces or data center protocols
  • Power & Noise analysis (EM/IR)
  • DFT integration

Key Requirements

  • 5+ years of hands-on experience in Chip Top Physical Design/Backend
  • Advanced process technologies (5nm, 3nm, and below)
  • B.Sc. or M.Sc. in Electrical Engineering
  • Proven experience executing complex block or chip-level projects

Work Rights

Not specified

Tailored Resume

Cover Letter