Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Supports SoC customers to ensure high-quality integration and verification of the IP block and drives quality assurance compliance for smooth IP-SoC handoff.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Skills & Requirements
Must-have
RTL design with Verilog/VHDL
IP block integration and verification
logic optimization for power/performance/area
design integrity for physical implementation
resolve failing RTL tests
Nice-to-have
strong communication and teamwork skills
highly motivated to learn
promote innovation and initiative
accountability and integrity
winning mindset
Key Requirements
Bachelors or Master’s degree in EE, CE or CS
Experienced using advanced verification methodologies