Sr Principal Design Engineer

Cadence

Multiple Locations
Rtl design using verilog
System verilog experience
Uvm based environment usage / debugging
The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence

Job Summary

  • The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence.
  • All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
  • We’re doing work that matters. Help us solve what others can’t.

Matching Summary

The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence.

Skills & Requirements

Must-have

  • RTL design using Verilog
  • System Verilog experience
  • UVM based environment usage / debugging
  • prior experience in RTL design
  • complex protocols implementation

Nice-to-have

  • making an impact on the world
  • solving what others can't
  • customer configurations clean
  • design clean for LINT and CDC

Key Requirements

  • BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI
  • experience as a design and verification engineer
  • recent work experience on RTL design and development
  • AXI3/4 experience
  • DDR Memory controller and protocol experience
  • Prior experience in IP development teams

Work Rights

Not specified

Tailored Resume

Cover Letter