Sr Principal Design Verification Engineer - Soc Verification

NXP USA INC.

Noida, India
On-site
Performance verification scenarios
Metrics analysis and cross correlation
System verilog, uvm methodology
NXP USA Inc. is seeking a Sr. Principal Design Verification Engineer for their performance verification team in Noida, India. The role focuses on developing performance verification scenarios for complex SOCs and requires strong technical skills in chip architecture, HDL, and various bus protocols

Job Summary

  • The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation, silicon.
  • The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.
  • Work with peer teams to correlate performance metrics across different platforms (TLM, RTL, Emulation, Silicon validation, applications).

Matching Summary

Match Score: 85

NXP USA Inc. is seeking a Sr. Principal Design Verification Engineer for their performance verification team in Noida, India. The role focuses on developing performance verification scenarios for complex SOCs and requires strong technical skills in chip architecture, HDL, and various bus protocols.

Skills & Requirements

Must-have

  • performance verification scenarios
  • metrics analysis and cross correlation
  • System Verilog, UVM methodology
  • Bus Protocols like AHB, AXI, CHI, ACE, APB
  • processor architecture, debug architecture
  • memory subsystems, caches, DDR controllers
  • programming skills in C/C++/Python

Nice-to-have

  • execute, analyze and debug on emulation
  • domain knowledge in Graphics/Multimedia/Networking IPs
  • cross domains collaboration

Key Requirements

  • Experience with HDL/HVL like Verilog, System Verilog, UVM methodology
  • Strong understanding Bus Protocols like AHB, AXI, CHI, ACE, APB
  • Understanding of processor architecture, debug architecture, Cache Coherency, NIC/NOC Architecture
  • Understanding of memory subsystems, caches, DDR controllers
  • Programming skills in C/C++/Python or other languages
  • User experience to execute, analyze and debug test cases on emulation platform would be an added advantage
  • Domain knowledge in at least some of the areas like Graphics/Multimedia/Networking IPs like PCIe, MIPI, Ethernet, USB etc.

Work Rights

Not specified

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