Research Engineer / Research Associate (FPGA Prototyping and ASIC Design Flow)

TUM CREATE LIMITED

Singapore, Singapore
Competitive salary commensurate with experience; m...
Not specified
Digital design foundation in rtl and timing
Hands-on fpga design flow experience
Programming skills in c/c++ or python
TUM CREATE LIMITED is seeking a Research Engineer/Research Associate to join their QUASAR project, focusing on FPGA prototyping and ASIC design flows for implementing Post-Quantum Cryptography within the RISC-V ecosystem. The role emphasizes cross-layer co-design and requires a strong foundation in digital design, FPGA flows, and programming skills

Job Summary

  • This role focuses on bridging FPGA-based system prototyping with manufacturable chip design using open-source EDA toolchains for the QUASAR project.
  • The position involves implementing Post-Quantum Cryptography within the RISC-V ecosystem to secure future digital infrastructure against quantum threats.
  • Candidates will benefit from hands-on experience with state-of-the-art open-source cores, close supervision in an international research environment, and competitive benefits including medical insurance.

Matching Summary

Match Score: 85

TUM CREATE LIMITED is seeking a Research Engineer/Research Associate to join their QUASAR project, focusing on FPGA prototyping and ASIC design flows for implementing Post-Quantum Cryptography within the RISC-V ecosystem. The role emphasizes cross-layer co-design and requires a strong foundation in digital design, FPGA flows, and programming skills.

Salary

Competitive salary commensurate with experience; Medical insurance included; Good amount of leave/vacation days

Skills & Requirements

Must-have

  • Digital design foundation in RTL and timing
  • Hands-on FPGA design flow experience
  • Programming skills in C/C++ or Python
  • RISC-V architecture or SoC design knowledge

Nice-to-have

  • Experience with Yosys OpenROAD OpenLane tools
  • Understanding of full ASIC synthesis to signoff flow
  • Interest in cross-layer architecture optimization
  • Background in EDA tool development or automation

Key Requirements

  • Degree in Electrical Engineering, Computer Engineering, or Computer Science

Work Rights

Not specified

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