Ivr / 3dic Design Flow Engineer (7102)

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San Jose, CA, US
Base: $153,000 - $250,000 py; bonus/equity: not sp...
On-site
Analog & mixed-signal design
3dic integration
Eda tool enablement
Lead development of Integrated Voltage Regulator (IVR) flows for advanced 3DIC technologies, critical for AI and HPC workloads

Job Summary

  • Lead development of Integrated Voltage Regulator (IVR) flows for advanced 3DIC technologies, critical for AI and HPC workloads.
  • Design and implement 3DIC-compatible analog flows by collaborating with EDA vendors and cross-functional teams, driving system-level integration into GPU and SoC platforms.
  • Work on cutting-edge challenges in high-performance computing, 2.5D/3DIC integration, and power distribution networks at the forefront of semiconductor innovation.

Matching Summary

Lead development of Integrated Voltage Regulator (IVR) flows for advanced 3DIC technologies, critical for AI and HPC workloads.

Salary

Base: $153,000 - $250,000 per year; Bonus/Equity: Not specified; Benefits: Comprehensive benefits

Skills & Requirements

Must-have

  • Analog & Mixed-Signal design
  • 3DIC integration
  • EDA tool enablement
  • TSMC PDKs
  • schematic and simulation methodologies

Nice-to-have

  • Python, Perl, SKILL, TCL, or Shell programming
  • Verilog/Verilog-A/AMS modeling
  • PDN extraction, SI/PI, thermal analysis
  • API development for EDA tools
  • machine learning for design optimization

Key Requirements

  • Master's or Ph.D. in Electrical Engineering or related field
  • 15+ years of experience in analog/mixed-signal design with PMIC/IVR focus
  • Strong knowledge of 3DIC design integration and analog flow development
  • Proficiency with Cadence/Synopsys/Ansys and other EDA tools

Work Rights

Not specified

Tailored Resume

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