Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing
Job Summary
Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Matching Summary
Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Skills & Requirements
Must-have
Static timing analysis
FPGA/SoC timing closure
Interface timing constraints
Timing convergence analysis
Industry standard EDA tools
Nice-to-have
Strong communication skills
Problem solving skills
Analytical skills
Key Requirements
3+ Years' experience
BE/MS/Phd in Electronics/Electrical Engineering
Tapeout experience in latest technology 10nm or lower