Serdes lead designer

Celerocommunicationsinc

Irvine, CA, United States
On-site
Serdes architecture and design
High-speed interconnect technology
Analog/mixed-signal circuit design
Celerocommunicationsinc is seeking a SerDes Lead Designer to develop and implement high-speed interconnect technology for next-generation AI applications. The role emphasizes architectural design, circuit topology, and system-level modeling, with a preference for candidates willing to work on-site in Irvine, CA

Job Summary

  • The role involves architecting and designing SerDes for next generation transceivers.
  • Candidates will oversee the development of system-level modeling and high-performance circuit design.
  • This position offers an amazing opportunity to work on disruptive technology powering next generation AI.

Matching Summary

Match Score: 85

Celerocommunicationsinc is seeking a SerDes Lead Designer to develop and implement high-speed interconnect technology for next-generation AI applications. The role emphasizes architectural design, circuit topology, and system-level modeling, with a preference for candidates willing to work on-site in Irvine, CA.

Skills & Requirements

Must-have

  • SerDes architecture and design
  • High-speed interconnect technology
  • Analog/mixed-signal circuit design

Nice-to-have

  • Experience with MATLAB and SystemVerilog
  • Leadership in lab validation
  • Understanding of signal integrity

Key Requirements

  • Experience in high-speed analog design
  • Knowledge of RX/TX equalization techniques
  • Familiarity with power, performance, area optimization

Work Rights

Not specified

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