Design Verification Lead Engineer

Cadence

Systemverilog assertions sva
Uvm environment development
Processor integration experience
The Lead DV Engineer focuses on the execution and technical management of verification projects to ensure comprehensive test coverage

Job Summary

  • The Lead DV Engineer focuses on the execution and technical management of verification projects to ensure comprehensive test coverage.
  • You will lead a focused team to develop UVM scoreboards, monitors, and complex functional coverage models for processor-specific interfaces.
  • The role requires managing automated regression environments and coordinating with design engineers to resolve complex RTL failures.

Matching Summary

The Lead DV Engineer focuses on the execution and technical management of verification projects to ensure comprehensive test coverage.

Skills & Requirements

Must-have

  • SystemVerilog Assertions SVA
  • UVM environment development
  • Processor integration experience
  • AMBA/PCIe protocol expertise
  • Automated regression management

Nice-to-have

  • Leadership and team management skills
  • Project planning and tracking
  • Scripting for flow automation
  • Microarchitectural bug resolution
  • Multi-protocol interface knowledge

Key Requirements

  • B.S/M.S in EEE degree
  • 5–8+ years hands-on VLSI verification experience
  • Strong command of SystemVerilog and UVM

Work Rights

Not specified

Tailored Resume

Cover Letter