Staff Physical Design Engineer

Analog Devices

San Jose, CA, US
Base: $154,841 to $232,261; bonus/equity: discreti...
Hybrid
Cadence digital implementation tools
Siemens calibre
Rtl-to-gdsii flow
This role involves leading the physical design, timing closure, and sign-off for complex, hierarchical eFPGA fabrics on advanced technology nodes

Job Summary

  • This role involves leading the physical design, timing closure, and sign-off for complex, hierarchical eFPGA fabrics on advanced technology nodes.
  • Key responsibilities include executing custom power grid planning, floorplanning, EM/IR analysis, and driving end-to-end hierarchical physical implementation using Cadence tools.
  • The position offers a competitive salary range of $154,841 to $232,261, a performance-based bonus, and comprehensive benefits including medical, dental, vision, and 401k.

Matching Summary

This role involves leading the physical design, timing closure, and sign-off for complex, hierarchical eFPGA fabrics on advanced technology nodes.

Salary

Base: $154,841 to $232,261; Bonus/Equity: discretionary performance-based bonus; Benefits: medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time

Skills & Requirements

Must-have

  • Cadence digital implementation tools
  • Siemens Calibre
  • RTL-to-GDSII flow
  • timing closure
  • power grid planning
  • hierarchical physical implementation

Nice-to-have

  • FPGA/eFPGA architecture
  • programmable logic optimization
  • flow development
  • CAD automation

Key Requirements

  • 8+ years of experience in physical design
  • B.S./M.S. in Electrical or Computer Engineering
  • Hands-on experience at 16nm/7nm/5nm or lower nodes
  • Strong understanding of UPF-based low-power flows
  • Skilled in Tcl and Python scripting
  • Experience with Calibre DRC/LVS

Work Rights

Export licensing review may be required for non-US citizens

Tailored Resume

Cover Letter