Analog Layout Engineer

Capgemini

San Francisco, CA, US
Base: $97,700 to $203,800 py; bonus/equity: not sp...
On-site
Analog/rf layout design
Finfet and deep sub-micron processes
Block-level and ip-level design
We are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization

Job Summary

  • We are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization.
  • Independently develop block‑level and IP‑level analog/RF layouts, partnering closely with circuit designers and global layout teams to drive designs from concept to tape‑out.
  • Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.

Matching Summary

We are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization.

Salary

Base: $97,700 to $203,800 per year; Bonus/Equity: Not specified; Benefits: Comprehensive package

Skills & Requirements

Must-have

  • Analog/RF layout design
  • FinFET and deep sub-micron processes
  • Block-level and IP-level design
  • Top-level integration
  • DRC, LVS, antenna, and verification issues

Nice-to-have

  • Collaborative global design and layout organization
  • End-to-end ownership
  • Technical leadership and mentoring

Key Requirements

  • 6+ years of analog/RF layout experience
  • Bachelor’s degree in Electrical Engineering
  • Experience with SerDes, ADC/DAC, PLLs

Work Rights

Not specified

Tailored Resume

Cover Letter