Soc/ip Design Verification Engineer

Intel

Bangalore, India
Hybrid
5+ years soc verification experience
Uvm/systemverilog testbench development
Coverage-driven verification methodology
The role involves owning the complete verification lifecycle for complex SoC and IP blocks from planning to signoff

Job Summary

  • The role involves owning the complete verification lifecycle for complex SoC and IP blocks from planning to signoff.
  • Candidates will architect scalable UVM environments and develop constrained-random test content to ensure high-quality silicon delivery.
  • This position requires close collaboration with design, architecture, firmware, and validation teams across multiple sites.

Matching Summary

The role involves owning the complete verification lifecycle for complex SoC and IP blocks from planning to signoff.

Skills & Requirements

Must-have

  • 5+ years SoC verification experience
  • UVM/SystemVerilog testbench development
  • Coverage-driven verification methodology
  • Debug skills in simulation and emulation
  • Scripting proficiency in Python and Shell

Nice-to-have

  • Experience with standard protocols like AXI PCIe
  • Assertion-based verification using SVA
  • Power-aware verification with UPF/CPF
  • Emulation and FPGA prototyping experience
  • Leadership and mentoring capabilities

Key Requirements

  • BS/MS in Electrical or Computer Engineering
  • Minimum 5 years of SoC/IP verification experience
  • Proficiency with Synopsys VCS or Cadence Xcelium simulators

Work Rights

Not specified

Tailored Resume

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