Senior Asic Design - Cisco Silicon One

Cisco UK

Caesarea, Israel
Rtl design experience
Verilog/systemverilog implementation
Full chip integration
Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development, covering the full spectrum of chip design

Job Summary

  • Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development, covering the full spectrum of chip design.
  • Leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible.
  • Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era, with limitless opportunities to grow and build.

Matching Summary

Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development, covering the full spectrum of chip design.

Skills & Requirements

Must-have

  • RTL design experience
  • Verilog/SystemVerilog implementation
  • Full chip integration
  • Timing methodology and analysis
  • Collaboration with verification engineers
  • Debug and root-cause analysis

Nice-to-have

  • MATLAB simulations
  • Bit-exact modeling environments
  • Mixed-signal systems
  • Clock Domain Crossing (CDC)

Key Requirements

  • B.Sc./M.Sc. in Electrical Engineering
  • RTL design experience
  • Familiarity with UVM
  • Familiarity with functional verification methodologies

Work Rights

Not specified

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