Front End Asic Rtl/logic Senior Design Engineer

Altera Corporation

Penang, Malaysia
10 years of asic frontend experience
Rtl coding proficiency using hdl languages
Knowledge of spyglass synthesis sta pt upf uvm spice dft
The role requires leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO

Job Summary

  • The role requires leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO.
  • Candidates must possess a minimum of 10 years of ASIC frontend experience with strong analytical and problem-solving abilities.
  • The position involves close collaboration with verification and back-end teams to ensure successful floor planning and timing closure.

Matching Summary

The role requires leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO.

Skills & Requirements

Must-have

  • 10 years of ASIC frontend experience
  • RTL coding proficiency using HDL languages
  • Knowledge of Spyglass Synthesis STA PT UPF UVM Spice DFT

Nice-to-have

  • Strong communication and leadership skills
  • Scripting knowledge desirable
  • Post Silicon debug and characterization support

Key Requirements

  • BS/MS or PhD in Electronics Engineering
  • Minimum 10 years of ASIC frontend experience
  • Proficiency with logic simulation and debug environments

Work Rights

Not specified

Tailored Resume

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