Soc/ip Design Verification Engineer

Intel Retiree Medical Plan Trust

Guadalajara, Mexico
Hybrid
Uvm/systemverilog development expertise
5+ years soc/ip design verification experience
Constrained-random test content creation
This role requires a hands-on engineer to drive verification for complex SoC/IP blocks across block, subsystem, and SoC levels

Job Summary

  • This role requires a hands-on engineer to drive verification for complex SoC/IP blocks across block, subsystem, and SoC levels.
  • Candidates must own the full verification lifecycle including planning, UVM environment architecture, test content creation, and coverage closure.
  • The position demands strong collaboration with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.

Matching Summary

This role requires a hands-on engineer to drive verification for complex SoC/IP blocks across block, subsystem, and SoC levels.

Skills & Requirements

Must-have

  • UVM/SystemVerilog development expertise
  • 5+ years SoC/IP design verification experience
  • Constrained-random test content creation
  • Coverage closure and debug skills
  • Python/Shell scripting for automation

Nice-to-have

  • Assertion-based verification (SVA) and formal methods
  • Power-aware verification with UPF/CPF
  • Emulation/FPGA prototyping experience
  • Cross-functional collaboration skills
  • Continuous improvement mindset

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • Unrestricted permanent right to work in Mexico
  • Advanced English proficiency required

Work Rights

Must have unrestricted, permanent right to work in Mexico

Tailored Resume

Cover Letter