Design Verification Engineer

Altera

San Jose, California, United States
$142.6k - $206.5k usd
On-site
Uvm-based testbenches
Systemverilog assertions (sva)
Pcie gen4/gen5/gen6 transactions
Responsible for verifying the correctness, performance, and compliance of FPGA and SoC designs, with a strong focus on PCIe subsystems

Job Summary

  • Responsible for verifying the correctness, performance, and compliance of FPGA and SoC designs, with a strong focus on PCIe subsystems.
  • Develop, implement, and maintain comprehensive UVM-based testbenches for PCIe IP, subsystems, and full-chip FPGA/SoC designs.
  • Mentor and provide technical guidance to junior and mid-level design verification engineers.

Matching Summary

Responsible for verifying the correctness, performance, and compliance of FPGA and SoC designs, with a strong focus on PCIe subsystems.

Salary

$142.6K - $206.5K USD

Skills & Requirements

Must-have

  • UVM-based testbenches
  • SystemVerilog assertions (SVA)
  • PCIe Gen4/Gen5/Gen6 transactions
  • constrained-random test environments
  • FPGA/SoC designs

Nice-to-have

  • CXL protocol layers
  • FPGA architecture familiarity
  • mentor junior engineers

Key Requirements

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related discipline
  • 8+ years of professional Design Verification experience
  • 4+ years of experience verifying PCIe IP or subsystems
  • 7+ years of experience writing SystemVerilog and UVM-based testbenches
  • 4+ years of experience developing constrained-random test environments

Work Rights

Not specified

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