Senior Design Verification Engineer

Analog Devices, Inc.

Valencia, Spain
System verilog and uvm
Metric driven methodology
Simulation and emulation
As a Senior Design Verification Engineer, you will play a key role in defining and driving the verification strategy, planning, and execution

Job Summary

  • As a Senior Design Verification Engineer, you will play a key role in defining and driving the verification strategy, planning, and execution.
  • You will be part of a highly skilled team that develops verification environments and re-usable components using System Verilog and UVM.
  • Partner with cross-functional teams (design, architecture, software, implementation) to ensure robust design quality and timely project execution.

Matching Summary

As a Senior Design Verification Engineer, you will play a key role in defining and driving the verification strategy, planning, and execution.

Skills & Requirements

Must-have

  • System Verilog and UVM
  • metric driven methodology
  • simulation and emulation
  • constrained-random and directed test cases
  • functional coverage models and assertions

Nice-to-have

  • evolving new verification methodologies
  • multi-site teams and 3rd party VIP
  • global semiconductor leader

Key Requirements

  • Master’s degree in Computer/Electrical engineering
  • strong background in digital design and design verification
  • Experience with object-oriented programming
  • Systemverilog/UVM, Python, Perl
  • Cadence, Synopsys, and/or Mentor tools
  • System and Digital modeling languages (MATLAB or SystemC)
  • design/verification tape-out cycle exposure

Work Rights

Not specified

Tailored Resume

Cover Letter