Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Supports SoC customers to ensure high-quality integration and verification of the IP block and drives quality assurance compliance for smooth IP-SoC handoff.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Skills & Requirements
Must-have
RTL design with Verilog and/or VHDL
IP design and verification
logic design and simulation
power, performance, area, and timing goals
Nice-to-have
advanced verification methodologies
constrained random verification
assertion based verification
functional coverage techniques
Perl, C++, Java and shell scripts
communication, initiative, innovation and teamwork
highly motivated to learn and adapt
Key Requirements
Bachelors or Master’s degree in EE, CE or CS, or equivalent
Familiarity or experience in RTL design
Familiarity or experience with RTL verification and timing analysis/closure