Senior Asic Design Verification Engineer Category Location Toronto, Ontario

Talentlab Inc

Toronto, Ontario, Canada
On-site
Uvm verification environment development
C/c++ integration with systemverilog dpi/pli
Pcie gen-3+ and ethernet vip experience
The role involves developing complex SoC verification environments for a leader in purpose-built connectivity solutions

Job Summary

  • The role involves developing complex SoC verification environments for a leader in purpose-built connectivity solutions.
  • Candidates must possess strong academic backgrounds in electrical engineering with at least two years of relevant industry experience.
  • The position requires independent test planning and collaborative debugging with RTL designers to ensure silicon quality.

Matching Summary

The role involves developing complex SoC verification environments for a leader in purpose-built connectivity solutions.

Skills & Requirements

Must-have

  • UVM verification environment development
  • C/C++ integration with SystemVerilog DPI/PLI
  • PCIe Gen-3+ and Ethernet VIP experience
  • Scripting automation with Perl or Python
  • Hybrid directed and constrained random testing

Nice-to-have

  • SoC kernel and device driver debugging
  • FPGA-based verification and emulation
  • DDR4/DDR5/HBM memory technology expertise
  • Physical Layer and Link Layer PCIe verification

Key Requirements

  • Bachelor's degree in Electrical Engineering required; Master's preferred
  • Minimum 2 years experience in Server, Storage, or Networking applications
  • Proven ability to work independently with minimal supervision

Work Rights

Not specified

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