Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Leads the Partial Reconfiguration (PR) Validation team and creates designs using HDLs and Altera IPs, verifying functionality and timing on FPGA Hardware Boards.
Collaborates with cross-functional teams to develop and improve validation strategies and resolve customer issues.
Matching Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
FPGA Partial Reconfiguration (PR) flow
Altera Quartus
VHDL, Verilog or SystemVerilog
HW debugging skills using SignalTap
AXI, PCIe, Ethernet, Avalon bus protocols
Nice-to-have
Compiler optimizations research
cross-functional team collaboration
customer issue resolution
Key Requirements
6+ years of relevant experience
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design