Senior Principal Software Engineer - Accelerated Verification Ip

Cadence

Base: $154,000 to $286,000 (california); bonus/equ...
Hybrid
Pcie protocol implementation
Cxl protocol expertise
Systemverilog or verilog development
The role involves designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution

Job Summary

  • The role involves designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution.
  • Engineers will work across hardware and software boundaries to ensure correctness, performance, and scalability in emulation flows.
  • The company offers competitive compensation including bonus, equity, and comprehensive benefits like 401(k) matching and medical plans.

Matching Summary

The role involves designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution.

Salary

Base: $154,000 to $286,000 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • PCIe protocol implementation
  • CXL protocol expertise
  • SystemVerilog or Verilog development
  • Hardware-software co-simulation
  • Emulation platform debugging

Nice-to-have

  • Customer enablement experience
  • Performance profiling skills
  • Cross-functional collaboration
  • Emerging interconnect knowledge

Key Requirements

  • BS degree with 10+ years experience OR MS with 7+ years OR PhD with 5+ years
  • Strong fundamentals in digital design and computer architecture
  • Experience with C/C++ programming

Work Rights

Not specified

Tailored Resume

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