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On-site
Develop dft strategy for hierarchical dft
Perform atpg and scan coverage debug
Experience with asic dft synthesis flow
The role involves developing a comprehensive DFT strategy for hierarchical designs and driving design fixes for quality improvements
Job Summary
The role involves developing a comprehensive DFT strategy for hierarchical designs and driving design fixes for quality improvements.
Candidates will perform Automatic Test Pattern Generation (ATPG) and verify scan content at both RTL and gate levels.
The position requires collaborating with Design, Verification, and Physical Design teams to manage mutual dependencies and ensure requirements are met.
Matching Summary
The role involves developing a comprehensive DFT strategy for hierarchical designs and driving design fixes for quality improvements.
Skills & Requirements
Must-have
Develop DFT strategy for hierarchical DFT
Perform ATPG and scan coverage debug
Experience with ASIC DFT synthesis flow
Nice-to-have
Familiarity with Mentor Tessent EDA tools
Experience in IP integration including MBIST
Knowledge of SoC cycles and silicon bringup
Key Requirements
Bachelor's degree in Electrical or Computer Engineering
4 years of experience in ATPG methods
Experience with multiple projects in DFT scan design