Soc Design Verification Lead

Altera

Bengaluru, Karnataka, India
Uvm methodology
System verilog language
Full chip verification
Lead SoC architecture verification, including creating verification strategy, developing test cases, and test benches using UVM methodology

Job Summary

  • Lead SoC architecture verification, including creating verification strategy, developing test cases, and test benches using UVM methodology.
  • Coordinate cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage verification plans and verify performance using system full applications.
  • Drive a team towards project execution and delivery, encompassing the complete verification life cycle from architecture to coverage closure.

Matching Summary

Lead SoC architecture verification, including creating verification strategy, developing test cases, and test benches using UVM methodology.

Skills & Requirements

Must-have

  • UVM methodology
  • System Verilog language
  • full chip verification
  • ARM based SoC verification
  • protocol experience (PCIe, Ethernet, USB, TSN)

Nice-to-have

  • scripting in Linux/Unix
  • Perl and/or Python proficiency
  • Design for Debug experience
  • cross-functional team coordination
  • dynamic environment flexibility

Key Requirements

  • 12+ years of experience
  • B.Tech/M.Tech in Electrical Engineering, Electronics, or related field
  • Experience with formal verification methods
  • Experience with post-silicon issue replication and debugging

Work Rights

Not specified

Tailored Resume

Cover Letter