Acquire knowledge of microarchitecture an ASIC unit by studying the specification and interacting with the logical design team
Job Summary
Acquire knowledge of microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
Monitor, analyze and debug simulation errors and monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
Competitive salary package, 10 Days of Public Holiday, 22 days of Earned Leave, 11 days for sick or caregiving leave, and Benefit Plans (Insurance).
Matching Summary
Acquire knowledge of microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
Skills & Requirements
Must-have
UVM verification methodology
SystemVerilog hardware verification
Constraint-Random verification environments
Coverage-Driven verification
simulation tools and coverage visualization
Nice-to-have
Curious, demanding and rigorous
Mastering object oriented programming
Effective in problems solving
Key Requirements
3-5 years experience
Bachelor’s degree (BE/B.Tech) or Master’s degree (ME/M.Tech)