Not specified (likely hybrid or onsite based on industry norms).
8-12 years physical design experience
Advanced node soc implementation (5nm/7nm)
Cadence innovus or synopsys icc2 expertise
Analog Devices, Inc. is seeking a Lead Physical Design Engineer with extensive experience in physical design implementation for complex digital SoCs. The ideal candidate will possess strong leadership skills and technical expertise in advanced-node designs, focusing on delivering high-quality results while mentoring a small team
Job Summary
The role combines deep hands-on implementation expertise with technical leadership for complex block and top-level physical design.
Candidates must drive timing closure, congestion resolution, and physical verification to meet PPA targets on advanced technology nodes.
The position requires leading a small group of engineers while defining hierarchical PNR strategies and integration guidelines for large SoCs.
Matching Summary
Match Score: 85
Analog Devices, Inc. is seeking a Lead Physical Design Engineer with extensive experience in physical design implementation for complex digital SoCs. The ideal candidate will possess strong leadership skills and technical expertise in advanced-node designs, focusing on delivering high-quality results while mentoring a small team.
Skills & Requirements
Must-have
8-12 years physical design experience
Advanced node SoC implementation (5nm/7nm)
Cadence Innovus or Synopsys ICC2 expertise
End-to-end floorplanning and routing ownership
Power grid and PDN methodology mastery
Nice-to-have
Strong mentoring and team leadership skills
Experience with DFT and STA collaboration
Bias toward scalable automated solutions
Ability to manage shifting priorities
Key Requirements
8-12+ years in physical design
Hands-on expertise with industry-standard PNR tools
Proven success closing challenging blocks on advanced nodes
Work Rights
Must be US Citizen, US Permanent Resident, or protected individual; others require export licensing review