Senior Physical Design Engineer

Cisco UK

Armenia
Rtl to gdsii implementation
Gate-level netlist synthesis
Floorplanning, placement, cts, routing
Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond

Job Summary

  • Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond.
  • You will be responsible for macro level RTL to gds implementation and signoff.
  • Beyond your technical work, you'll be part of a culture that values mentorship, celebrates success, and supports your growth.

Matching Summary

Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond.

Skills & Requirements

Must-have

  • RTL to GDSII implementation
  • gate-level netlist synthesis
  • floorplanning, placement, CTS, routing
  • Static Timing Analysis (STA)
  • physical verification, formal verification
  • Electromigration (EM) and IR-drop (IR) analysis

Nice-to-have

  • collaboration with Front-End teams
  • mentorship and career growth
  • automation and efficiency improvements
  • AI era solutions

Key Requirements

  • 6+ years ASIC design and verification experience
  • Bachelor's or Master's degree
  • Proven expertise in ASIC physical design
  • Advanced knowledge of block-level synthesis
  • First-hand experience with Synopsys and Cadence tools

Work Rights

Not specified

Tailored Resume

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