The Principal Verification Engineer will join an experienced Controller IP Team to design state-of-the-art DDR memory controllers for Datacenter, Edge computing, Automotive, and AI applications
Job Summary
The Principal Verification Engineer will join an experienced Controller IP Team to design state-of-the-art DDR memory controllers for Datacenter, Edge computing, Automotive, and AI applications.
Key responsibilities include architecting verification environments, developing self-checking regressions with UVM-SV scoreboards, and managing verification plans using Cadence vManager tools.
This role requires close collaboration with design engineers to debug complex test scenarios while adhering to ISO-9001 technical review meetings and checklists.
Matching Summary
The Principal Verification Engineer will join an experienced Controller IP Team to design state-of-the-art DDR memory controllers for Datacenter, Edge computing, Automotive, and AI applications.
Skills & Requirements
Must-have
10-15 years microelectronics experience
UVM-SV Scoreboard development
Metric Driven Verification (MDV)
SystemVerilog Assertions implementation
Verilog RTL Design background
Nice-to-have
Front-end design tools LINT Synthesis CDC
ISO-9001 and ISO-26262 quality processes
AXI and/or CHI protocol experience
Jenkins automated regression management
Strong interpersonal communication skills
Key Requirements
Degree in Electrical/Electronic Engineering or related discipline
10-15 years experience in microelectronics/EDA industry