Static Timing Analysis (sta) Engineer – (lead Or Senior)

Boeing

El Segundo, CA, United States
Lead, level 4: $146,200 – $197,800; senior, level ...
On-site
Static timing analysis (sta)
Asic and fpga timing closure
Synopsys primetime or cadence tempus
Responsible for STA analysis and convergence throughout the ASIC cycle, finding solutions for intricate timing paths

Job Summary

  • Responsible for STA analysis and convergence throughout the ASIC cycle, finding solutions for intricate timing paths.
  • Generate timing constraints for multiple ASICs and FPGAs, including tool-independent constraints for synthesis, place & route, and static timing analysis.
  • Collaborate with other electronics groups, IP teams, EDA vendors, and Foundries for timing convergence and design closure.

Matching Summary

Responsible for STA analysis and convergence throughout the ASIC cycle, finding solutions for intricate timing paths.

Salary

Lead, Level 4: $146,200 – $197,800; Senior, Level 5: $176,800 - $239,200; Benefits: Not specified

Skills & Requirements

Must-have

  • Static Timing Analysis (STA)
  • ASIC and FPGA timing closure
  • Synopsys Primetime or Cadence Tempus
  • Python, TCL, Perl, Unix shell scripting

Nice-to-have

  • innovative thinking
  • ambitious and thrive in technology development
  • work full spectrum from research through flight insertion
  • supportive of innovative thinking

Key Requirements

  • Bachelor of Science degree in Engineering, Computer Science, Data Science, Mathematics, Physics, or Chemistry
  • 5 years of experience with timing closure on ASICs and FPGAs
  • Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out
  • Proficiency using Synopsys Primetime (or Cadence Tempus) and Synopsys Design Compiler (or Cadence Genus)
  • Ability to work with large physical design team

Work Rights

Must have U.S. Security Clearance

Tailored Resume

Cover Letter