Understanding of design, architecture and clocking
Writing constraints
Responsible for STA and timing closure activities of Intel SoCs/Partitions
Job Summary
Responsible for STA and timing closure activities of Intel SoCs/Partitions.
Your tasks may include but not limited to Understanding of Design, Architecture and Clocking, Interaction with FE/DFT/Verification teams, Writing constraints, understanding synchronous - asynchronous paths, Clock domain crossing issues, Timing closure, Generating timing ECOs Timing signoff - Debugging/troubleshooting of timing issues in a design.
You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise.
Matching Summary
Responsible for STA and timing closure activities of Intel SoCs/Partitions.
Skills & Requirements
Must-have
STA and timing closure
Understanding of Design, Architecture and Clocking
Writing constraints
Clock domain crossing issues
Timing signoff
Debugging/troubleshooting of timing issues
Hands-On experience with Primetime
Scripting skills in TCL/Perl/Shell
Nice-to-have
Strong initiative
Analytical/problem solving skills
Team working skills
Ability to multitask
Self-motivated
Driving new methodologies
Key Requirements
10+ Years of relevant experience
Skills in Physical Implementation and Timing Closure
Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering