Senior Pre-silicon Verification Engineer

Intel Corporation

Hillsboro, Oregon, US
Base: $141,910.00-232,190.00 usd; bonus/equity: st...
Hybrid
Uvm
Systemverilog
Mixed-signal verification
We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs

Job Summary

  • We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs.
  • This role combines digital verification expertise with mixed-signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high-quality clock generation solutions.
  • We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs.

Matching Summary

We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs.

Salary

Base: $141,910.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • UVM
  • SystemVerilog
  • mixed-signal verification
  • clock generator IP verification
  • AMS simulation techniques

Nice-to-have

  • analytical and problem-solving skills
  • collaboration across teams
  • technical documentation and communication
  • RTL development experience

Key Requirements

  • 3+ years of experience in Design Verification
  • 3+ years of experience in scripting languages
  • Bachelor's degree in Engineering
  • Post graduate degree preferred

Work Rights

Not specified

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